jrIDE bus loading / max side cars

[MattCarp]

I am working on a variation of the jrIDE.

Chuck Terra made an interesting post in this forum about the order in which he installed sidecars with respect to the jrIDE.

Here's the other post viewtopic.php?f=1&t=937

Based on my analysis of jrIDE,
-> the address bus connects to 5 devices: 2 RAM, ROM, CPLD1 (u4), and CPLD2 (u6)
-> the data bus connects tosix devices: all of the same as the address bus, plus the real time clock

According to the PCjr Tech Ref, the PCjr bus should be able to support 5 standard TTL loads. This should be a sinking of (5 * 1.6mA =) 8 mA on a low output (I-ol) and sourcing (5 * 40 uA=) 200 uA on a high output (I-oh). Looking at the data sheets of the devices on the jrIDE, I only come up with 34 uA of input current on either a low or high. This suggests that the current drive of the chips are totally fine.

I believe (but am not 100% sure about) the current requirements of the chips on the jrIDE design are so low because they're CMOS devices.

Chuck's scope trace showed a 4V maximum voltage on a data line?

I find that curious, since the chips on the jrIDE should have enough sinking/sourcing power? I'd expect that you get close to 5V when a signal is high.

(For reference, the proper TTL input voltages should be low from 0 - 0.8V, and high at 2.0- 5V).

I would think, though, that because the design doesn't have any components related to buffering the bus signals or terminating the signal lines, there's an impedance mismatch, and we should be seeing some ringing - both overshoot and undershoot. If we add additional cards, I don't think we will hit current limits (because the jrIDE is so low), but I think the impedance mismatches will cause additional ringing.

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I don't have a jrIDE myself, but what I would find interesting is:

A scope trace of a data line, and an address line (either A0, A1, or A6).

MEMR/W would also be mildly interesting, as those lines hit 4 devices in the jrIDE design (ROM, 2 RAM, and CPLD1)

I'd like to see that, zoomed in a little, to clearly see the square wave. I'd like to see the maximum voltage as well as the amount of overshoot and undershoot.

One suggestion is to say "just put bus buffers (74LS244 / '245) on all these signals", but the problem is that unless I move to surface mount technology, there isn't a lot of room to do that, especially if you have to do that with the address bus (20 lines!).

[prpplague]

I don't have a jrIDE myself, but what I would find interesting is:
A scope trace of a data line, and an address line (either A0, A1, or A6).
MEMR/W would also be mildly interesting, as those lines hit 4 devices in the jrIDE design (ROM, 2 RAM, and CPLD1)
I'd like to see that, zoomed in a little, to clearly see the square wave. I'd like to see the maximum voltage as well as the amount of overshoot and undershoot.
One suggestion is to say "just put bus buffers (74LS244 / '245) on all these signals", but the problem is that unless I move to surface mount technology, there isn't a lot of room to do that, especially if you have to do that with the address bus (20 lines!).

i'm looking to do this type of testing with my PCjr bus expansion board with multiple cards. it's on my agenda in coming weeks!

https://hackaday.io/project/171799-ibm- ... -backplane
https://hackaday.io/project/171128-ibm- ... sion-board