Mike's PCjr Page

I'd also like to propose that, whatever we do for ethernet, we connect it to IRQ 1. That'll make it a nice PCjr exclusive design.

jmetal88 wrote:Actually, the board design I already posted has a full 640k on board, for the 736k upgrade. I could remove the 128k SRAM and the extra address decode logic for that chip, and we'd have more room to add ethernet components. I don't know if it would be enough room, yet, but we could give it a shot.

Do you have a BOM - I could look up the current requirements of each chip. That'll help us understand if the CP2200 is even a possibility from a power perspective.

Yeah, here's a BOM for a board containing just the XT-IDE circuit and 512k SRAM. That's where I have the design sitting right now, waiting on input from you guys.

Thanks.

Ok - I think first, we'll need to design a more powerful power supply for the PCjr!

In looking through all the data sheets, the total max current is as high as 537 mA! That's if I choose max values for everything, which really wouldn't happen. If I choose typical values on the data sheets I referenced where they specified typical values, the typical current is 410 mA.

By substituting the worst 74LS chips (245, 573, 688) with 74ALS, we can cut over 150mA and get closer to the 250 mA territory. Using 74HCT could save even more power, but I'd want to be certain we can make that substitution as some parameters may be different.


Part Qty Supply current (mA, max; mA typ-max) Max current (mA) Typ current (mA)

74LS32 1 4.9-9.8 9.8 4.9
74LS30 1 1.1 1.1 1.1
74LS04 1 3.6-6.6 6.6 3.6
74LS138 1 7-11 11 7
74LS245 1 64-95 95 64 ALS type is 58 mA
74LS573 3 50 150 150 ALS typ is 48 mA total
74LS688 2 40-65 130 80 ALS typ is 24 mA total
74LS154 1 9-14 14 9
X28C64 1 30-60 60 30
512k SRAM 1 60 60 60

total current 537.5 409.6


The CP2200 uses 60 mA but can use as much as 155 mA when transmitting. That seems to just fit. However, this doesn't leave any other power on the bus, say for a parallel port sidecar. I'd like to have another 25-50 mA safety margin.

Are there any lower power substitutes for the SRAM and EEPROM?

I'm not sure which SRAM you're looking at, as the SRAM provided by the BOM generation seems to be pretty generic, but this is the chip I was looking at using:

http://www.jameco.com/webapp/wcs/stores ... 1927617_-1

This is the same chip I used in my homemade 512k internal upgrade. Supposedly the average current draw is 30ma and the maximum is 60ma.

I haven't really looked into other EEPROMs yet, as that's the EEPROM specified in the original XT-IDE schematic.

My table is completely unreadable, but I used 60 mA for the SRAM. If it's somewhere around 30-45 mA is more typical, that'll give us the safety margin we need.

I'd still want to be choosy on the EEPROM, as every little bit will help.

It's actually not completely unreadable, but I must admit I made that post after coming back from a birthday party last night, and I was quite drunk.

You know, I bet we could save even more power if we went with this guy's revision of the XT-IDE:

http://dangerousprototypes.com/docs/XT_ ... controller

He's gone through and done the thing in CPLDs, so that's fewer chips to worry about, and hopefully less current draw. It does mean that we need to program more than just the BIOS, though.

I guess the CPLD device is the modern day equivalent of the PLA ...

That approach has been on my todo list to investigate since we are going to be adding a bit more address decode logic.

Cool. I'll take a little break from this, I think, and let you check that out.

I did catch a mistake in my current design today, and I corrected it, but I think that's all I'll do for now. I'm still looking into doing an internal RAM upgrade and the three ISA slot thing with 512k on-board. They'll be cheap to prototype since both designs fit under the specifications for that Chinese site that does PCB prototypes at $28 for 10 boards.