Mike's PCjr Page

I never auto-route a final design. Every one I've ever tried is just plain bad. They sometime are useful for suggesting paths. But most wont even do basic gate swapping. Some of the higher end tools have descent parallel bus routing. Almost essential for impedance matching. But even those require lo...

I might. It would be the third EDA tool I would have to use on a regular basis. Two are bad enough. And I used yet another, PCAD, in my last job. I've looked at KiCAD before, and unless there isn't another option, Eagle is so much better imo.

After working on this a bit tonight, I could accommodate both A and B if I put the 40 pin .1" header inside the posts. It would rule out a flash module, but it would allow for a cable. I guess you could call it an option E. I'm not real keen on the CF adapter unless I go option D in which case ...

On the subject of board changes, I'm still under an area limitation with Eagle. I don't think I can fit a 2.5" 2mm 44-pin right angle board mount and a .1" 40 pin header too. Let's discuss options for Rev.P2. A) Keep it the way it is -> 2.5" HD w/ 44-pin 2mm right angle header and scr...

Optimized the in-line asm now: extern void _xfer_sector_in (uint16_t far *dst); #pragma aux _xfer_sector_in = \ "push ds" \ "lds si, dword ptr ide_sector" \ "mov cx, 0x100" \ "cld" \ "rep movsw" \ "pop ds" \ parm [di es] \ modify [si es di ...

It just occurred to me, my transfer buffer is probably in lower 128 KB memory as it is a normal DOS .EXE (~12KB). I'll re-run the test with the dest pointer above 128K.

EDIT: NM, didn't seem to make a difference.

Things haven't been very productive today. My board is failing as I didn't realize how bad PLCCs were at insert/remove reliability. I've been popping the chip in and out a lot since it's easier for me to program it w/ my eeprom burner. I'll have to build up one of the JTAG cables Monday and continue...

So preliminary test = ~230 KB/s raw reads. That's un-optimized but also w/o interrupt overhead.

I hit a road bump last night when I was changing the PLD code to do it. All of a sudden the RTC stopped working. I've tried just about everything to fix it, but haven't been able to. I think maybe a cell has gone out on the smaller PLD, but not 100% sure. Everything else still works including RAM, f...

It's going to take some testing. I'm wondering if I/O mapping would be more efficient since while you can do a rep insw, you can't do a rep movsw since you actually don't want si to auto increment on each loop. I'll just have to test things out. The good news is the current layout has both sets of s...