Mike's PCjr Page

Stupid question.. but if the register maps are changing so that IDE drive regs are no longer mapped 1:1 into I/O space, why map them in I/O space at all? 8-bit I/O access always adds 4 wait cycles. If you left a hole in the ROM image, decoded the IDE chip selects to the base of the hole and masked o...

It's looking like I'm going to at least build 3 of the boards I layed out above. DorkbotPDX takes in hobbyist board designs until they have enough for a full route and retain panel, then order 3 at a time. It's $10 per square inch for 4 layer boards for three copies. So that's only $10 a piece for t...

You are right, I had 29/21 flipped incorrectly. But yes DMACK should be grounded since it's an input to the drive.

First I'm not sure why the XT-IDE schematic had them the way they did. There must have been a reason and until I find out why, I'm uncomfortable with my choices. They were pulling up/down outputs from the drive that were not connected on the controller end like DMA request. I don't see how that does...

jmetal88, where did you find the mechanicals for the board? (i.e. offsets for holes and connector)

The danger of programmable devices is you can easily get carried away. The 22V10s are ~$2.50 each so they are not cheap and adding the second just to reduce the chip count by 2 is probably not cost effective. But it helps layout and power, allows the I/O address selection to be non-linear, and half ...

Couple other optimizations: A) Take hargle's advice and drop the extra small RAM. Eliminates components and is unneeded. B) Where one PAL is good, two are better. The first can do the comparison of A17=0, A18=1, A19=1. Route A4..9, A13..16, IO/M, and the 8 selects from the DIP switch/pull-up bank in...

Speaking of theoretical, after thinking of this thread a while, I wondered if it would be possible to design a board that literally fit into the footprint of an 8088? For systems (not just the PCjr) that were ether space constrained around the processor socket or had limited or no ISA expansion slot...

What do you mean wrong pin out? Pin 12 is GND, 24 is +5V, 1-11 & 13 are inputs only and the rest inputs or outputs. Signal assignments are made by pin number in the code. BTW when you start routing, you can move any Pin-I/O assignment around within those constraints and then change it in the PLD...

I put a RTC on my ISA prototype carrier boards to evaluate and spent about $2 total not including a 2032 battery. But it was SMD. Maxim/Dallas is proud of their stuff.