Alright, here's an up-to-date component layout. I already added in the 44-pin connector in a position that should make it easy to plug in one of those flash modules. Unfortunately, I don't think there's room for a full CF converter or connector in there. If you guys really want it, though, there might be a way to add in a generic 50-pin connector (that could fit a CF) aimed out the back, but you'd have to be careful not to insert the CF card the wrong way around.jmetal88 wrote:I did, but it's not up to date with today's changes yet. I'll get back to you when I have it more current.Lutiana wrote:Have you got an actual board layout that you can post?
XT-IDE on PCjr
Re: XT-IDE on PCjr
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- JR-IDE-V2-brd.pdf
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Re: XT-IDE on PCjr
I must not have an updated schematic. Is V2 the latest? There's a ton of problems with it:
1) U5 has 2 floating inputs (R3 & R4).
2) I'm not sure why you have U6 pins R2, R3, and R5 pulled up and then shorted to GND. The pull-ups do nothing but waste power and require a second network that could be eliminated.
3) Your RAM address decoding seems a bit wonky too. ALE is normally a low signal. It pulses high for half a bus clock at the start of an access cycle. It's generally not used for chip selection. You might as well wire the decoder gates to ground.
4) The placement of the parts on the PCB looked a little too anal. Did you auto-route or something? I can't imagine that's where the parts would have landed if it were hand routed.
5) U10 gates A3 from the ISA side to A0 on the IDE side
6) Lots of other address decode logic is radically different from Andrew and hargle's original board. Especially latching up to the upper set of data lines. The design as laid out wont work with the stock XT-IDE BIOS. eg. Did you mean to route A0 to the XORs catching the CS_IDE output and it's complement? And I'm not sure if the current XT-IDE BIOS is accessing the upper IDE data bus, but I don't see a flip-flop on the upper latch control like in the XT-IDE design.
I stopped looking after all those problems.
1) U5 has 2 floating inputs (R3 & R4).
2) I'm not sure why you have U6 pins R2, R3, and R5 pulled up and then shorted to GND. The pull-ups do nothing but waste power and require a second network that could be eliminated.
3) Your RAM address decoding seems a bit wonky too. ALE is normally a low signal. It pulses high for half a bus clock at the start of an access cycle. It's generally not used for chip selection. You might as well wire the decoder gates to ground.
4) The placement of the parts on the PCB looked a little too anal. Did you auto-route or something? I can't imagine that's where the parts would have landed if it were hand routed.
5) U10 gates A3 from the ISA side to A0 on the IDE side
6) Lots of other address decode logic is radically different from Andrew and hargle's original board. Especially latching up to the upper set of data lines. The design as laid out wont work with the stock XT-IDE BIOS. eg. Did you mean to route A0 to the XORs catching the CS_IDE output and it's complement? And I'm not sure if the current XT-IDE BIOS is accessing the upper IDE data bus, but I don't see a flip-flop on the upper latch control like in the XT-IDE design.
I stopped looking after all those problems.
Re: XT-IDE on PCjr
My RAM address decoding is fine. ALE is hooked up to an output enable, as is IO/M. Both must be low before any decoding of the address even occurs. If both are low, A16-A19 are decoded to their 16 outputs, 8 of which are used to determine Chip Select for the SRAM.
ALE is hooked up to the output enable because of this remark in the SRAM datasheet:
"WE#, CE# must be high during all address transitions."
If you don't understand why I've done this, read the datasheets for the AS6C4008 and 74154 chips. This part of the circuit has been hand wired and hooked up to my PCjr before (actually without even wiring up IO/M, just with ALE), and it does indeed work.
As for the rest of the design, apart from changing it to the 3 DIP switch address selection, it's a direct copy of the XT-IDE version 2 schematic. Oh, except for the U5 floating inputs thing, that's something my schematic program seems to have done on it's own, and I fixed it yesterday (just didn't upload a new one yet).
I can fix issue 2 pretty easily, it's just a result of my changing from the 5-jumper to the 3-DIP-switch design. At this point, it'd probably be best to just remove the pull-up resistor packs and just use individual pull-up resistors only for the inputs controlled by the switch.
Issue 5, I believe, is supposed to be that way. Part of the 16-bit addressing. It's not something I did to the design (I think).
For issue 6 (and the above), please check my design against the XT-IDE version 2 design that Hargle posted earlier. It should be an exact copy of that. It's not supposed to work with the original XT-IDE BIOS, a new version should be done for the XT-IDE version 2, which should then be modified for use with the PCjr. I could have gone with the original XT-IDE design, but Mike is set on using 16-bit I/O, and I agree that that should be done.
I'm glad you're taking a look, though, it worried me when I caught a couple of mistakes on there yesterday and I realized nobody had pointed them out, yet!
Oh, as for the PCB, my idea there was to make assembly as painless as possible. I am auto-routing, but I am not auto-placing. I hand-placed the components, and I purposely tried to use even spacing and had everything oriented the same way. I tried to use the 'rats nest' net list visual as an aid for placement, but I'm not too experienced at this. Really, I don't think I should be the one making this design, but I know the software and I didn't see any other volunteers (and I also have a ton of free time right now), so... yeah.
ALE is hooked up to the output enable because of this remark in the SRAM datasheet:
"WE#, CE# must be high during all address transitions."
If you don't understand why I've done this, read the datasheets for the AS6C4008 and 74154 chips. This part of the circuit has been hand wired and hooked up to my PCjr before (actually without even wiring up IO/M, just with ALE), and it does indeed work.
As for the rest of the design, apart from changing it to the 3 DIP switch address selection, it's a direct copy of the XT-IDE version 2 schematic. Oh, except for the U5 floating inputs thing, that's something my schematic program seems to have done on it's own, and I fixed it yesterday (just didn't upload a new one yet).
I can fix issue 2 pretty easily, it's just a result of my changing from the 5-jumper to the 3-DIP-switch design. At this point, it'd probably be best to just remove the pull-up resistor packs and just use individual pull-up resistors only for the inputs controlled by the switch.
Issue 5, I believe, is supposed to be that way. Part of the 16-bit addressing. It's not something I did to the design (I think).
For issue 6 (and the above), please check my design against the XT-IDE version 2 design that Hargle posted earlier. It should be an exact copy of that. It's not supposed to work with the original XT-IDE BIOS, a new version should be done for the XT-IDE version 2, which should then be modified for use with the PCjr. I could have gone with the original XT-IDE design, but Mike is set on using 16-bit I/O, and I agree that that should be done.
I'm glad you're taking a look, though, it worried me when I caught a couple of mistakes on there yesterday and I realized nobody had pointed them out, yet!
Oh, as for the PCB, my idea there was to make assembly as painless as possible. I am auto-routing, but I am not auto-placing. I hand-placed the components, and I purposely tried to use even spacing and had everything oriented the same way. I tried to use the 'rats nest' net list visual as an aid for placement, but I'm not too experienced at this. Really, I don't think I should be the one making this design, but I know the software and I didn't see any other volunteers (and I also have a ton of free time right now), so... yeah.
Re: XT-IDE on PCjr
Updated schematic here. This one fixes the issues that I know I caused, and that I'm sure are issues. Sorry about the file name being V2 every time - this is not the revision number, this is just supposed to signify that it's based on the XT-IDE version 2 schematic. I haven't really given anything a revision number, so just go by the upload date. 
EDIT: Oh yeah, I should probably mention, I decided to just put all the address pull-ups through the one resistor pack, rather than moving to individual resistors there.
EDIT: Oh yeah, I should probably mention, I decided to just put all the address pull-ups through the one resistor pack, rather than moving to individual resistors there.
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- JR-IDE-V2.pdf
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Re: XT-IDE on PCjr
All of the problems I've listed are actually valid. I'm not making them up. You need to check again. I'm just trying to help.
1) Fixed. Your new address decode windows are now: 0x30x, 0x32x, 0x34x, and 0x36x. Though the chip selects will go active on memory accesses to that range during early boot up - which is also a problem on XT-IDE btw. Also see #7 below.
2) Fixed.
3) I know your RAM board worked. You've entirely missed what I'm trying to tell you about ALE. At this point I would suggest reading a book on ISA. ALE is always going to be 0V except for 1/2 a bus clock at the start of each cycle. It's a pointless signal since all the address lines on the connector are already latched on the system board.
4) Persists.
5) Still wrong and will prevent your board from working
6) My eyesight is getting bad in my old age, but you're not even close to the XT-IDE Schematic
New items:
7) AEN is also a pointless signal on the PCjr as there is no 8237a. Nevermind that HLDA != AEN anyway. Wire pin 1 on U5 to GND or invert IO/_M or AND or XOR /IOM & /IOR. See note above for #1.
8) Remove unconnected nets from the IDE headers and ISA header. Called-out net names that don't go anywhere hurt readability.
9) hargle and Andrew have both mentioned they would like to use more than 8K of flash space for future revs of XT-IDE. Is there a ROM window limitation at C0000 or C8000 on the Jr that's limiting you to only exposing 8K of the flash?
10) Your symbol for the 74154 should have the enables indicated as active low as they really are active low.
1) Fixed. Your new address decode windows are now: 0x30x, 0x32x, 0x34x, and 0x36x. Though the chip selects will go active on memory accesses to that range during early boot up - which is also a problem on XT-IDE btw. Also see #7 below.
2) Fixed.
3) I know your RAM board worked. You've entirely missed what I'm trying to tell you about ALE. At this point I would suggest reading a book on ISA. ALE is always going to be 0V except for 1/2 a bus clock at the start of each cycle. It's a pointless signal since all the address lines on the connector are already latched on the system board.
4) Persists.
5) Still wrong and will prevent your board from working
6) My eyesight is getting bad in my old age, but you're not even close to the XT-IDE Schematic
New items:
7) AEN is also a pointless signal on the PCjr as there is no 8237a. Nevermind that HLDA != AEN anyway. Wire pin 1 on U5 to GND or invert IO/_M or AND or XOR /IOM & /IOR. See note above for #1.
8) Remove unconnected nets from the IDE headers and ISA header. Called-out net names that don't go anywhere hurt readability.
9) hargle and Andrew have both mentioned they would like to use more than 8K of flash space for future revs of XT-IDE. Is there a ROM window limitation at C0000 or C8000 on the Jr that's limiting you to only exposing 8K of the flash?
10) Your symbol for the 74154 should have the enables indicated as active low as they really are active low.
Re: XT-IDE on PCjr
I know you're trying to help. I really appreciate it. I just feel I have a valid reason for doing some of the things you've pointed out, and you're not quite understanding me yet. Rest assured, I am trying to take in everything that you're saying, and I will not push forward with any kind of production until we're in agreement on everything. 
3) No, I think you've missed what I'm trying to tell you about ALE. ALE is only high while there is a transition between addresses. I need that on the output enable of the 74154 so that Chip Select is high during address transitions. It doesn't matter that the addresses are latched, they still have to change sometime, or you'd be looking at the same 8 bits of RAM the whole time. I looked at the timing diagrams of the 8088 very carefully before I decided to wire up ALE.
4) I don't think there's any point in doing anything about this yet. I'll try to optimize the design after we get the schematic details hammered out.
5,6) You're not really reading me here. I wanted you to compare my schematic to the XT-IDE version 2 schematic. If there is a discrepancy at that point, it's a problem I caused. What you're looking at is an older copy of the version 1 schematic. Hargle posted the version two schematic directly to this thread. Here's the link again:
http://www.waste.org/~winkles/XT-IDE_V2-sch_may10.pdf
7)I'll get to work on that. I wired AEN to HLDA because Mike's page on the ISA adapter has it done that way. It did bother me that they were named differently, but that was the only information I had at the time.
8)I'll get to work on that, too.
9)Read Mike's comments earlier in the thread. All we have to work with is C0000 to CFFFF, and the BIOS fits in 4k of space. It'd be a waste to use more than 8k. I know the schematic shows a 28C256, but I'm just using that because I didn't want to generate a new symbol for a 28C64, and they have nearly identical pinouts. I am planning to fix the component name at some point.
10)I'm just using the 74154 symbol that came with KiCAD. It never really bothered me that the pins didn't have proper symbols on them, as I know they're active low and wired them as such.
3) No, I think you've missed what I'm trying to tell you about ALE. ALE is only high while there is a transition between addresses. I need that on the output enable of the 74154 so that Chip Select is high during address transitions. It doesn't matter that the addresses are latched, they still have to change sometime, or you'd be looking at the same 8 bits of RAM the whole time. I looked at the timing diagrams of the 8088 very carefully before I decided to wire up ALE.
4) I don't think there's any point in doing anything about this yet. I'll try to optimize the design after we get the schematic details hammered out.
5,6) You're not really reading me here. I wanted you to compare my schematic to the XT-IDE version 2 schematic. If there is a discrepancy at that point, it's a problem I caused. What you're looking at is an older copy of the version 1 schematic. Hargle posted the version two schematic directly to this thread. Here's the link again:
http://www.waste.org/~winkles/XT-IDE_V2-sch_may10.pdf
7)I'll get to work on that. I wired AEN to HLDA because Mike's page on the ISA adapter has it done that way. It did bother me that they were named differently, but that was the only information I had at the time.
8)I'll get to work on that, too.
9)Read Mike's comments earlier in the thread. All we have to work with is C0000 to CFFFF, and the BIOS fits in 4k of space. It'd be a waste to use more than 8k. I know the schematic shows a 28C256, but I'm just using that because I didn't want to generate a new symbol for a 28C64, and they have nearly identical pinouts. I am planning to fix the component name at some point.
10)I'm just using the 74154 symbol that came with KiCAD. It never really bothered me that the pins didn't have proper symbols on them, as I know they're active low and wired them as such.
Re: XT-IDE on PCjr
3) I see what you are doing now and we're saying the same thing about ALE. I never said it wouldn't work. It's just odd seeing it that way as the traditional means for ISA decode is by command strobes. Your solution is 8-bit ISA centric and could also be done by taking MEMR/MEMW through either a spare XOR or AND instead.
5) My apologies about the schematic reference. I'm looking at the current XT-IDE one now. I wasn't aware there was code support to shift the address ranges up by a bit.
9) Understood & 640K is enough for everybody!
5) My apologies about the schematic reference. I'm looking at the current XT-IDE one now. I wasn't aware there was code support to shift the address ranges up by a bit.
9) Understood & 640K is enough for everybody!
Re: XT-IDE on PCjr
Alright, this version should have a couple more things fixed. I still haven't got around to fixing the symbols, as that's a little bit more of a hassle than moving net names around. And, as I've said before, I have a tendency to overlook my own mistakes, so I can't be absolutely certain that I have things exactly the way we need them yet.
I had to add another inverter IC, as the current design (inverting IO/M for the U5 output enable) requires seven inverter gates. I changed a couple of the symbol references to make more even use of the two inverter chips (four gates on one chip, three on the other). I also changed U6 output enable to connect straight to IO/M instead of HLDA.
Anyway, this schematic shows what I've done so far.
I had to add another inverter IC, as the current design (inverting IO/M for the U5 output enable) requires seven inverter gates. I changed a couple of the symbol references to make more even use of the two inverter chips (four gates on one chip, three on the other). I also changed U6 output enable to connect straight to IO/M instead of HLDA.
Anyway, this schematic shows what I've done so far.
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Re: XT-IDE on PCjr
I've been kind of busy lately so you have managed to run quite a bit past me, and it's hard to keep track of what is going on in the posts. For the sake of getting me back up to sync, how does that last design differ from the original XT-IDE that I am using for the BIOS work? (Besides the SRAM .. did you swap address lines or do anything else?)
Re: XT-IDE on PCjr
Yeah, the address decode logic for the IDE interface is swapped around. A0 and A3 are the affected lines, and I have them routed just like in the schematic Hargle posted earlier in the thread. That should make the address space sequential so that 16 bit reads and writes are possible. Look at the 74ls138 and the surrounding logic on my schematic to note the specific changes.Brutman wrote:I've been kind of busy lately so you have managed to run quite a bit past me, and it's hard to keep track of what is going on in the posts. For the sake of getting me back up to sync, how does that last design differ from the original XT-IDE that I am using for the BIOS work? (Besides the SRAM .. did you swap address lines or do anything else?)
EDIT: Oh yeah, and I also locked it down to a more limited range of addresses, if you hadn't gathered that. For the I/O, 300h, 320h, 340h, and 360h are selectable via the first two DIP switches. The ROM address is switchable between C0000 and C8000 via the third DIP switch. I chose this scheme because the window on the Booster fits three DIP switches.