XT-IDE on PCjr

[jmetal88]

Alright, I hope I did the NPN thing right. When I start working with discrete components over digital ICs, I start to get a little bit more unsure of myself.

Updated schematic attached.

[alanh]

You are inverting the polarity of the signal. You either need to cascade another inverting NPN or use a discrete 7404 output on the base if one opens up (don't add another just for that). You also need to switch the R7/R4 resistance values. If layout makes adding it difficult, worry about it. That circuit (Q1/R7/R4) is a prototype test thing only. It probably won't be stuffed on any boards, but if during test someone finds it is needed, it costs nothing to have the traces already layed out on the board.

Not sure what R1 is doing there either.

BTW have you done any layout sanity checks so far? By current count there are 17 ICs, 2 of them 600 mil W, 2 headers, and other incidentals. That's quite a lot.

[jmetal88]

You are inverting the polarity of the signal. You either need to cascade another inverting NPN or use a discrete 7404 output on the base if one opens up (don't add another just for that). You also need to switch the R7/R4 resistance values. If layout makes adding it difficult, worry about it. That circuit (Q1/R7/R4) is a prototype test thing only. It probably won't be stuffed on any boards, but if during test someone finds it is needed, it costs nothing to have the traces already layed out on the board.

Not sure what R1 is doing there either.

BTW have you done any layout sanity checks so far? By current count there are 17 ICs, 2 of them 600 mil W, 2 headers, and other incidentals. That's quite a lot.

I'll just remove the NPN for now until I can figure out how it's actually working.

I already explained R1, it's there so CS1 isn't floating when the computer is off. The RTC chip will still be running off the backup battery, and CS1 has to be pulled low before it will enter standby mode.

[jmetal88]

Here's a layout sanity check for you. Routing will be a bit complicated, but there is room for all the components.

EDIT: That 3.6V should just say 3V, by the way. I momentarily forgot the voltage of a CR2032 and generated the PDF before changing it on the board and schematic.

[alanh]

I would be shocked if that layout auto routes even @ 6/6 with only 2 layers. And if it did, you'd have more vias than pin holes. Your component placement looks a little scarey. Very simple changes would go along way there (eg. staggering the RAM/ROM pins, orienting the IDE data bus buffer and latches like the reference I posted a while back, etc). You probably should also move the 47uF closer to the supply - ideally have the +5V trace go through the 47uF positive pad before anywhere else. A 22uF where you have the 47 wouldn't be a bad idea either.

And I wouldn't push a board house to their spec'd limits either. Generally the closer you get to the limit of capability, the worse quality you get back. Take the design rules they give you and back them off a tad. Where were you thinking of getting prototype PCBs made?

The best way to learn efficient board layout is attempt to manual route everything. Starting out you will probably rip up and restart 20 times for every successful section, but the added time/frustration is very helpful from an educational point of view.

I looked over the schematic pretty well. I don't see anything else wrong with it.

[jmetal88]

I would be shocked if that layout auto routes even @ 6/6 with only 2 layers. And if it did, you'd have more vias than pin holes. Your component placement looks a little scarey. Very simple changes would go along way there (eg. staggering the RAM/ROM pins, orienting the IDE data bus buffer and latches like the reference I posted a while back, etc). You probably should also move the 47uF closer to the supply - ideally have the +5V trace go through the 47uF positive pad before anywhere else. A 22uF where you have the 47 wouldn't be a bad idea either.

And I wouldn't push a board house to their spec'd limits either. Generally the closer you get to the limit of capability, the worse quality you get back. Take the design rules they give you and back them off a tad. Where were you thinking of getting prototype PCBs made?

The best way to learn efficient board layout is attempt to manual route everything. Starting out you will probably rip up and restart 20 times for every successful section, but the added time/frustration is very helpful from an educational point of view.

I looked over the schematic pretty well. I don't see anything else wrong with it.

I know that's a terrible layout - I put it together in a hurry just to see if all the components would fit on the board.

I'll definitely take whatever suggestions you can give me, though. Like I said, I know the program, but I have no experience actually producing this stuff.

[jmetal88]

And I wouldn't push a board house to their spec'd limits either. Generally the closer you get to the limit of capability, the worse quality you get back. Take the design rules they give you and back them off a tad. Where were you thinking of getting prototype PCBs made?

I guess I didn't answer this in the last post.

I wanted to get them from Advanced Circuits, through their program at 33each.com. That's $33 for each two-sided board, which I think is about the best we could do for a small prototype run on boards around this size.

[jmetal88]

Well, I'm gonna let the autorouter have at it, to see what it comes up with, I think. Then, I'll make adjustments to placement and other things based on how much trouble it has (and I'll try to manually route the result).

[jmetal88]

Alright, as it currently sits, I have about 130 vias on the unoptimized autorouted board. I'm using 12 mil width/10 mil spacing on signal lines and 24-mil width power traces.

I've seen the autorouter go down from 130 vias down to 20 or 30 after optimization, though, but that takes several hours to complete so I'll have to report back later on that.

I'm actually doing a manually routed version of the board simultaneously, but all I have done so far are the memory chips to the sidecar bus.

[alanh]

I started going down a CPLD route to sorta see what was possible. The only practical part choice (through hole / 5V / and still in production) is the Atmel ATF150x line. Unfortunately they are stingy with their synthesis license and even if I did get one it would only be a 6-month eval. So I'm stuck writing code in CUPL with only a logic level simulator (no timing) and no signal path delay computations that I'm aware of. So tracing each signal path through the generated netlist and adding up each gate's propagation delay from the data sheet is very tedious and I have limited time. The nice thing about the CPLD is it's in-circuit programmable with a parallel cable and a PC. So someone with a DB-25M shell, wire and pin sleeves could program it themselves after building. It drops the design down to just 6 ICs (even adding another for RAM) and allows the use of the ubiquitous DS12887+. It also opens up the possibility of fast PIO or bus mastering from IDE in the future. At only $5 with socket, it would be a cost saver too. And the entire layout atm literally fits between the 4 interior posts; leaving room to plug in an industrial flash module plugged directly on the board with a R/A 40 pin IDE header.

I'm going to see how far along I get, but I don't want to raise expectations until I have something a bit more solid. I'm still trying to throw some employer weight around (we just bought over a million AVRs) and pull a Verilog compiler and timing simulator from my rep at Atmel. For now it's probably a good idea to continue down your route and build a few prototypes once you are comfortable with the effort.

On the bright side, I am becoming quite the expert in CUPL. Which now days is about the only semi-maintained tool chain language for simple PLDs. And Atmel is about the only company still making them. Was kinda sad when Lattice finally killed off the GAL line.