Internal 512k expansion?

[jmetal88]

I came across this video on Youtube, and it looks like the owner of this PCjr managed to make or find and internal 512k RAM upgrade.

http://www.youtube.com/watch?v=HxwP66skxjM

In the comments section, he says the RAM is on a special board together with an NEC V20 that fits straight into the CPU socket.
I tried to post a comment asking for either details on the construction or pictures of the board, but it seems I'm 'pending approval' of some sort before the comment shows up.

In the meantime, does anyone have any ideas of how one would connect extra RAM in the PCjr straight to the 8088? I thought about using a 74154 as a crude address decoder for the top four address lines, which would seem to work for adding eight 8-bit chips, but I noticed only SRAM tends to have the chip enable pin, and it's next to impossible to get 64kx8 SRAM in DIP. Also I notice the PCjr uses DRAM by default, and I am unsure if that poses some kind of issue.

The other thing that somewhat concerns me is the fact that, on the 8088 and V20, the first eight address lines and the eight data lines share the same pins. I don't know if that would require some kind of filtering or what. I have very, very little electronics experience and I've never really tried to design a circuit before so I don't really know what I'm doing here.

If anyone has any ideas, I'd love to hear them!

[Brutman]

Look at the web site .. I think I've got nearly every memory expansion documented.

I didn't have the patience to sit through the video, but it is either a jrHotshot or a Legacy "The One" board. These type of boards generally plug into the CPU socket, and then the CPU plugs into the board. It allows them to handle memory references above 128K, while letting the main system board handle the references for the first 128K on the motherboard. Some of the boards add a clock and calendar too, probably because there was enough left over real-estate on the board.

If you had to do something like this today you would use a single 512K SRAM chip - that gets rid of need for a separate DRAM controller. You'd have just a few chips for address decoding and then the SRAM chip.

[jmetal88]

He doesn't even show it in the video, he just mentions it in the comments, so if you don't want to sit through it, don't bother.

I do see the info on your site now, though.

I'd like to think about how one might accomplish putting together a board with a single 512K SRAM chip though, as I'd ideally like something I could wire together myself rather than something I'd have to spend a lot of time hunting down.

[jmetal88]

Ah, here's a nice looking and cheap 512kx8 SRAM chip: http://www.jameco.com/webapp/wcs/stores ... SF&CID=GMC

I think I'll study up on address decoding and look at how it's handled on the PCjr motherboard to see if I can't figure out a good way to interface that chip.

[jmetal88]

I decided to go a slightly different direction with this. Here's what I've come up with so far.

I traced the 20 address lines, 8 data lines, memory read, and memory write from the sidecar bus to the legs of five ICs located in front of the CPU on the motherboard. Picking up the signals this way eliminated the need for much of the address decoding circuitry as the data and address lines are already separated.

To decide when to select the 512k chip, I'd like to use one of the 3-input NOR circuits on a 7427 to set the enable line of the 512k chip low if any of the address lines A19, A18, or A17 are high. A17 and A18 would also have to be connected to the 512k chip's address lines.

I'm thinking everything else would be a direct connection to the RAM chip. I want to piggyback sockets over the five ICs involved and use DIP headers with ribbon cable to get the signals and make the mod easily removable.

So, to you folks with more electronics and PCjr experience than I, should my idea work?

EDIT: Apparently, I can't count. The signals come of six ICs, not five.

[Brutman]

The six ICs that you traced the sidecar bus to are probably the address latches, and not purely for address decode. The 8088 and 8086 use the same pins for both addresses and data, so the address has to be latched before the data is driven.

I'd pick up some reference material before hacking - the machines can be fragile when you do this kind of tinkering.

[jmetal88]

The six ICs that you traced the sidecar bus to are probably the address latches, and not purely for address decode. The 8088 and 8086 use the same pins for both addresses and data, so the address has to be latched before the data is driven.

I'd pick up some reference material before hacking - the machines can be fragile when you do this kind of tinkering.

Yes, that is what they are, the address latches. I don't know accurate terms for everything yet.]

Well, four of them are address latches, I guess one of them is the data latch(?), and I don't know what the sixth one is. I count two 74ls373s, two 74ls244s, one 74ls245 (this is where the data lines come from), and one 74ls257 (memory read and write are connected to this).

When I was looking at examples of small 8088-based circuits on the internet, all of them used latches to access memory, so I thought it would be easiest to pull of the latches already inside the PCjr.

If I go anywhere with this it probably won't be for a few weeks anyway, I'm still waiting on a keyboard and the official power transformer for my machine. Things like this are fun to think about anyway, though.

[jmetal88]

After sleeping on it, I realize a 3-input NOR is going to be inadequate for address decoding. It would turn the chip on for the proper address ranges, but it would not turn the chip off at address ranges reserved above the chip.

So, I've gone back to the idea of using the 74154 4-bit decoder to decode A16-A19. I'll feed the outputs 2-9 of the 74154 into the two 4-input NAND gates in a 7420, and I'll feed the 2 outputs of the 7420 into one of the NOR gates in a 7402. This should result in the chip enable line only being held low when addresses 20000 to 9FFFF are being accessed.

It would also be possible to replace the 7420+7402 with a single CD4068, but I figure since I already have the 7420, 7402, and 74154 on hand, I'll save myself a few cents and use what I already have.

[jmetal88]

Alright, I'm trying to make sure I think this through pretty thoroughly. According to the SRAM chip's datasheet, both Write Enable and Chip Enable must be held high during an address transition. Write enable is completely controlled by the PCjr, and I have to assume it was designed well enough to already be held high during address transitions.

Chip enable, however, is being handled by the address decode circuit I came up with. I have figured out I can force it high by setting one of the enable lines on the 74154 high. After looking at the 8088 datasheet and the datasheet for the 74ls373 latches, I've determined that during an address transition, the ALE signal from the 8088 should be high. I'm thinking that, in that case, if I connect pin 11 of one of the PCjr's address latches to one of the enable lines on the 74154, I should get the desired behavior of forcing Chip Enable on the SRAM high during address changes.

Feel free to chime in, anyone, if I appear to be missing anything.

[Brutman]

It's been ages, possibly decades since I dealt with address decode logic.

I'd chip in now, but I'm pre-occupied with a major bathroom renovation. I'm not sure how many other hardware hackers with time on their hands are lurking around ...