Mike's PCjr Page

OK, here's one with the Epson clock chip added in, too. I added another 74ls245 to it so I could have something to generate the four low signals in the upper address bus (since it's a four bit chip). I suppose it isn't strictly necessary, since we'd just be masking off the top four bits in software anyway, but to me it feels like the 'safe' thing to do.

I also corrected an error in the previous schematic where I forgot to have the IDE data bus turn on in memory space - it was still only doing so in I/O space.

EDIT: I made a mistake in this one regarding CS1 of the RTC chip. It should be connected to GND through a 10k resistor and VCC through a 1k resistor. That way, it gets a logic high with the machine on, and a non-floating logic low with the machine off (so the chip knows to go into standby for battery-backed operation).

EDIT 2: Oh, and Alan, I do eventually intend to follow what you did in your PLD schematic and replace the 74ls573 being used in the unlatched state with a 74ls245. Makes more sense to me.

I think that '573 was only being used to provide enough drive current for those signals. I'm not sure why a '245 wasn't used initially.

My only comment so far is it looks like the switches select one of 8 16KB windows between C0000 and DFFFF. 8KB of the flash is mapped in the lower half. The IDE register map sits at the start of the upper half. And the RTC registers sit at every other +64 byte offset within the upper half. Is my understanding accurate?

Also you have nothing breaking up the chip select assertion for IDE, ROM, and RTC. The only terms feeding into the production of those signals are A[19:4] and IO/M which for continuous access ranges are not going to change across successive bus cycles. You are using ALE to ensure /RAM_CS pulses between bus cycles. You need to either use that or an AND of /MEMRD & /MEMWR for all of the chip selects.

alanh wrote: My only comment so far is it looks like the switches select one of 8 16KB windows between C0000 and DFFFF. 8KB of the flash is mapped in the lower half. The IDE register map sits at the start of the upper half. And the RTC registers sit at every other +64 byte offset within the upper half. Is my understanding accurate?

Hmm... No, that shouldn't be what's going on. The RTC registers should be right above the IDE register map.

OK, I see what you're looking at, now. No, the reason it doesn't work the way you've interpreted it is because I hooked up the A0-A2 inputs of the 74ls138 backwards. If I hooked them up forwards, the RTC chip enable would be coming out output 1, pin 14.


As for introducing ALE, you're right, I should be doing that. I just didn't think about it since it wasn't in the original XT-IDE design (but I suppose that's because it wasn't memory mapped).

OK, here we go!

I added an ALE signal in a couple of places that should make sure the chip selects are off when ALE is high, and I swapped in the 74ls245. I put it in backwards compared to your design, however, so I could just ground the direction pin instead of adding a resistor to VCC.

I see my mistake on the '138. You are indeed correct.

As for chip selects, yes successive I/O IDE reads/writes would either hit different CS strobes on the IDE connector when doing word fetches or be interleaved with a memory access for the next instruction. That's changed now.

Also you have the buffered IDE_A0 going into A0 on the RTC - which is actually buffered from A3. Not sure if you intended this or not. It will reorder your RTC registers in the same fashon as IDE.

alanh wrote:I see my mistake on the '138. You are indeed correct.

As for chip selects, yes successive I/O IDE reads/writes would either hit different CS strobes on the IDE connector when doing word fetches or be interleaved with a memory access for the next instruction. That's changed now.

Also you have the buffered IDE_A0 going into A0 on the RTC - which is actually buffered from A3. Not sure if you intended this or not. It will reorder your RTC registers in the same fashon as IDE.

Whoops! That's a typo, thanks for pointing that out!

OK, let's try this again.

I'm glad I have someone catching my mistakes on this!

With memory mapped IDE, it might be a good idea to tie the ready lines together - ideally with an NPN or darlington.

I just caught another mistake on my part. I left IOR and IOW going into the 74ls245 instead of changing them to MEMR and MEMW.

alanh wrote:With memory mapped IDE, it might be a good idea to tie the ready lines together - ideally with an NPN or darlington.

That might indeed be a good idea. I think I'll work that in.